PRU ICSS INTC on TI SoCs
========================

Each PRUSS has a single interrupt controller instance that is common to both
the PRU cores. Most interrupt controllers can route 64 input events which are
then mapped to 10 possible output interrupts through two levels of mapping.
The input events can be triggered by either the PRUs and/or various other PRUSS
internal and external peripherals. The first 2 output interrupts (0 & 1) are
fed exclusively to the internal PRU cores, with the remaining 8 (2 through 9)
connected to external interrupt controllers including the MPU and/or other
PRUSS instances, DSPs or devices.

The K3 family of SoCs can handle 160 input events that can be mapped to 20
different possible output interrupts. The additional output interrupts (10
through 19) are connected to new sub-modules within the ICSSG instances.

This interrupt-controller node should be defined as a child node of the
corresponding PRUSS node. The node should be named "interrupt-controller".
Please see the overall PRUSS bindings document for additional details
including a complete example,
    Documentation/devicetree/bindings/soc/ti/ti,pruss.txt

Required Properties:
--------------------
- compatible           : should be one of the following,
                             "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
                                                 AM335x family of SoCs,
                                                 AM437x family of SoCs,
                                                 AM57xx family of SoCs
                                                 66AK2G family of SoCs
                             "ti,icssg-intc" for K3 AM65x & J721E family of SoCs
- reg                  : base address and size for the PRUSS INTC sub-module
- interrupts           : all the interrupts generated towards the main host
                         processor in the SoC. The format depends on the
                         interrupt specifier for the particular SoC's Arm
                         parent interrupt controller. A shared interrupt can
                         be skipped if the desired destination and usage is by
                         a different processor/device.
- interrupt-names      : should use one of the following names for each valid
                         host event interrupt connected to Arm interrupt
                         controller, the name should match the corresponding
                         host event interrupt number,
                             "host_intr0", "host_intr1", "host_intr2",
                             "host_intr3", "host_intr4", "host_intr5",
                             "host_intr6" or "host_intr7"
- interrupt-controller : mark this node as an interrupt controller
- #interrupt-cells     : should be 1. Client users shall use the PRU System
                         event number (the interrupt source that the client
                         is interested in) as the value of the interrupts
                         property in their node

Optional Properties:
--------------------
The following properties are _required_ only for some SoCs. If none of the below
properties are defined, it implies that all the PRUSS INTC output interrupts 2
through 9 (host_intr0 through host_intr7) are connected exclusively to the
Arm interrupt controller.

- ti,irqs-reserved     : an array of 8-bit elements of host interrupts between
                         0 and 7 (corresponding to PRUSS INTC output interrupts
                         2 through 9) that are not connected to the Arm
                         interrupt controller.
                           Eg: AM437x and 66AK2G SoCs do not have "host_intr5"
                               interrupt connected to MPU
- ti,irqs-shared       : an array of 8-bit elements of host interrupts between
                         0 and 7 (corresponding to PRUSS INTC output interrupts
                         2 through 9) that are also connected to other devices
                         or processors in the SoC.
                           Eg: AM65x and J721E SoCs have "host_intr5",
                               "host_intr6" and "host_intr7" interrupts
                               connected to MPU, and other ICSSG instances


Example:
--------

1.	/* AM33xx PRU-ICSS */
	pruss: pruss@0 {
		compatible = "ti,am3356-pruss";
		reg = <0x0 0x80000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		...

		pruss_intc: interrupt-controller@20000 {
			compatible = "ti,pruss-intc";
			reg = <0x20000 0x2000>;
			interrupts = <20 21 22 23 24 25 26 27>;
			interrupt-names = "host_intr0", "host_intr1",
					  "host_intr2", "host_intr3",
					  "host_intr4", "host_intr5",
					  "host_intr6", "host_intr7";
			interrupt-controller;
			#interrupt-cells = <1>;
			ti,irqs-shared = /bits/ 8 <0 6 7>;
		};
	};
